1. Field of the Invention
The present invention relates to semiconductor memory devices which comprise a plurality of memory cells each having a MOS transistor and a MOS capacitor, and more specifically, to a semiconductor memory device which is free from a soft error problem.
2. Description of the Prior Art
A dynamic RAM (hereinafter referred to as RAM), which comprises memory cells each having one transistor and one capacitor, has been widely used and the recent tendency of the D-RAM is its higher degree in integration and miniaturization. For the purpose of miniaturization of the D-RAM, it is essential that the memory cell has reduced capacitance in the cell capacitor. However, with the reduced capacitance of the cell capacitor, when subjected to .alpha. ray irradiated from its package or the like, the D-RAM generates minority carriers in a semiconductor substrate and flow of such minority carriers into a storage node of the cell capacitor causes a troublesome soft error.
As a method of reducing the soft error to a practically negligible extent, it has been proposed to provide an error detecting and correcting circuit (ECC circuit) on a D-RAM chip and this method is now at its trial and test stage.
Reliable detection and correction of an error can be made by increasing the redundancy of information bits to be stored, which increase in the number of redundant bits and resulting complication of the ECC circuit inevitably require an increase in the chip area, thus hindering improvement of integration of the D-RAM.
At the current stage of integration and miniaturization, when subjected to irradiation of a single .alpha. ray, a cell array will generate a single soft error for one column according to selection of one word line. However, when the integration degree increases and adjacent cells become closer, it is expected that a plurality of cells in one column of the cell array generate soft errors in response to incidence o the single .alpha. ray. Simultaneous removal of such a plurality of soft errors requires a larger ECC circuit and more redundant bits than the case where a single soft error occurs, which increases chip area, cost and number of logical elements necessary for the ECC circuit, thus increasing access time.